fix to initialisation in reflections module propagated to other branches

2014-06-10 14:03:41 +00:00 · 2014-06-10 14:03:41 +00:00 · 5a5406a5cf
commit 5a5406a5cf
parent e74ec6eecb
1 changed files with 2 additions and 1 deletions
--- a/src/reflections.f90
+++ b/src/reflections.f90
@ -32,7 +32,8 @@ subroutine inters_linewall(xv,kv,rw,zw,nw,sint,normw)
  integer :: i,j,ni,iint
  real(r8), dimension(2) :: si,ti
  real(r8) :: drw,dzw,xint,yint,rint,l,kxy
-  real(r8) :: tol=sqrt(epsilon(1.0_r8))
+  real(r8) :: tol
+  tol=sqrt(epsilon(1.0_r8))
  sint=huge(sint)
  iint=0
  normw=0.0_r8