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fix to initialisation in reflections module propagated to other branches

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Lorenzo Figini 2014-06-10 14:03:41 +00:00
parent e74ec6eecb
commit 5a5406a5cf
1 changed files with 2 additions and 1 deletions
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src/reflections.f90
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@ -32,7 +32,8 @@ subroutine inters_linewall(xv,kv,rw,zw,nw,sint,normw)
integer :: i,j,ni,iint integer :: i,j,ni,iint
real(r8), dimension(2) :: si,ti real(r8), dimension(2) :: si,ti
real(r8) :: drw,dzw,xint,yint,rint,l,kxy real(r8) :: drw,dzw,xint,yint,rint,l,kxy
real(r8) :: tol=sqrt(epsilon(1.0_r8)) real(r8) :: tol
tol=sqrt(epsilon(1.0_r8))
sint=huge(sint) sint=huge(sint)
iint=0 iint=0
normw=0.0_r8 normw=0.0_r8